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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Features
DigitalClarityTM CMOS Imaging Technology Ultra low-power, low cost CMOS image sensor Superior low-light performance Simple two-wire serial interface Auto black level calibration Window Size: VGA, programmable to any smaller format (QVGA, CIF) * Programmable Controls: Gain, frame rate, left-right and up-down image reversal, window size and panning * * * * * *
MT9V011
Micron Part Number: MT9V011P11ST
Table 1:
Key Performance Parameters
TYPICAL VALUE
1/4-inch (4:3) 3.58mm(H) x 2.688mm (V), 8.4mm Diagonal 640H x 480V 5.6um x 5.6um RGB Bayer Pattern Electronic Rolling Shutter (ERS) 13.5 MPS/27 MHz 30 fps at 27 MHz Programmable up to 60 fps Programmable up to 90 fps 10-bit, on-chip 1.9 V/lux-sec (550nm) 60dB 45dB 2.8V 0.25V 70mW at 2.8V, 20pF load, 27 MHz, 30 fps -20C to +60C 28-Pin PLCC
PARAMETER
Optical Format Active Imager Size Active Pixels Pixel Size Color Filter Array Shutter Type Max. Data Rate/Master Clock Frame VGA (640x480) Rate CIF (352x288) QVGA (320x240) ADC Resolution Responsivity Dynamic Range SNRMAX Supply Voltage Power Consumption Operating Temperature Packaging
Applications
* * * * Cellular phones PDAs PC Cameras Toys and other battery-powered products
Description
The Micron(R) Imaging MT9V011 is a VGA-format with a 1/4-inch CMOS active-pixel digital image sensor. The active imaging pixel array is 649H x 489V. It incorporates sophisticated camera functions on-chip such as windowing, column and row mirroring. It is programmable through a simple two-wire serial bus interface and has very low power consumption. The MT9V011 features DigitalClarity, our breakthrough, low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advantages of CMOS.
The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a VGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock which is synchronous with valid data.
09005aef80c6407f MT9V011_external_DS_1.fm - Rev. A 8/04 EN
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(c)2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Frame Timing Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Two-Wire Serial Interface Sample Read and Write Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Eight-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Eight-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Pixel Integration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Pixel Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Digital Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 True Decimation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Column Mirror image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Column and Row Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Line Valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Recommdended Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Propagation Delays for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
09005aef80c6407f MT9V011TOC.fm - Rev. A 8/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc.
Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Out Diagram - 28-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .13 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .14 Readout of 4 Pixels in Normal and Zoom 2x Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Readout of 8 Pixels in Normal and 2x Decimation Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Readout of 6 Pixels in Normal and Column Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Readout of 6 Rows in Normal and Row Mirror Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Readout of 8 Pixels in Normal and Column Skip Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Different Line Valid Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Acknowledge Signal Timing After an 8-bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Acknowledge Signal Timing After an 8-bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Spectral Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Die Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 28-Pin PLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
09005aef80c6407f MT9V011LOF.fm - Rev. A 8/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc.
Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Constant Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Frame Time - Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Vertical Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Recommended Gain Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
09005aef80c6407f MT9V011LOT.fm - Rev. A 8/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc.
Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 1: Block Diagram
Control Register APS Array 668H x 496V
Serial I/O
Timing and Control
Analog Processing
ADC
Data Out
Figure 2: Typical Configuration (Connection)
VDD VAA
1K 1.5K RESET_BAR 10F Two-wire serial bus Master Clock SDATA SCLK
VDD VAA VAAPIX
DOUT(9:0) FRAME_VALID LINE_VALID PIXCLK CLK_IN SCAN_EN OE_BAR
DGND
STANDBY
DGND
AGND
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc.
AGND
Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 3: Pin Out Diagram - 28-Pin PLCC
FRAME_VALID LINE_VALID
PIXCLK
SDATA
AGND VAA 12 AGND 13 VAAPIX 14 SCAN_EN 15 RESET_BAR 16 STANDBY 17 NC 18 OE_BAR
SCLK
11 10
19 20 21 22 23 24
DOUT9 DOUT8 DOUT7 DOUT6 DOUT5
NC
9
8
7
6
5 4 CLK_IN 3 DOUT0 2 DOUT1 1 VDD 28 DGND 27 DOUT2 26 DOUT3 25
DOUT4
Table 2:
PIN NUMBER 12 14 1 28 11,13 4 19 16 15 8 17 9 3 2 27 26 25 24 23
Pin Descriptions
NAME VAA VAAPIX VDD DGND AGND CLK_IN OE_BAR RESET_BAR SCAN_EN SCLK STANDBY SDATA DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 TYPE Power Power Power Ground Ground Input Input Input Input Input Input Bi-directional Output Output Output Output Output Output Output DESCRIPTION Analog Power (2.8V). Pixel Power (2.8V). Digital Power Supply (2.8V). Digital Ground. Analog Ground. Master Clock into sensor (27 MHz maximum). Output_Enable_Bar pin. When HIGH: disables the pixel data output drivers. Asynchronous reset of sensor when LOW. All registers assume factory defaults. Tie to Digital Ground. Serial Clock. When HIGH: disables the imager. Serial Data I/O. Pixel Data Output Bit 0, D0 (LSB). Pixel Data Output Bit 1, D1. Pixel Data Output Bit 2, D2. Pixel Data Output Bit 3, D3. Pixel Data Output Bit 4, D4. Pixel Data Output Bit 5, D5. Pixel Data Output Bit 6, D6.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 2:
PIN NUMBER 22 21 20 6 7 5 10 18
Pin Descriptions (continued)
NAME DOUT7 DOUT8 DOUT9 FRAME_VALID LINE_VALID PIXCLK NC NC TYPE Output Output Output Output Output Output DESCRIPTION Pixel Data Output Bit 7, D7. Pixel Data Output Bit 8, D8. Pixel Data Output Bit 9, D9 (MSB). Active HIGH during frame of valid pixel data. Active HIGH during line of selectable valid pixel data (see Reg0x20 for options). Pixel Clock Output. Pixel data outputs are valid during rising edge of this clock. Frequency = 1/2 (master clock). No connect. No connect.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Pixel Data Format Pixel Array Structure
The MT9V011's pixel array is 668 columns by 496 rows. The first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. The last column and the last row of pixels are also optically black. The black row data is used internally for automatic black level adjustment. There are 649 columns by 489 rows of optically active pixels, which provides a four-pixel boundary around the VGA (640 x 480) image to avoid boundary affects during color interpolation and correction. The additional active column and additional active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel, as shown in Figure 4.
Figure 5: Pixel Color Pattern Detail (Top Right Corner)
column readout direction black pixels Pixel (18, 6) (First Optical clear pixel)
...
G row readout direction B ... G B G B
R G R G R G
G B G B G B
R G R G R G
G B G B G B
R G R G R G
G B G B G B
Figure 4: Pixel Array Description
6 black rows (0, 0)
Output Data Format
1 black column
VGA (640 x 480) + 4 pixel boundary for color correction + additional active column + additional active row = 649 x 489 active pixels
18 black columns
(667,495)
1 black row
The MT9V011 image data is read-out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 6. The amount of horizontal and vertical blanking is programmable through Reg0x05 and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure. See "Output Data Timing" on page 9 for the description of FRAME_VALID timing.
...
The MT9V011 uses the RGB Bayer color pattern. Even numbered rows contain green and red color pixels, and odd numbered rows contain blue and green color pixels. Likewise, even numbered columns contain green and blue color pixels, and odd numbered columns contain red and green color pixels.
Figure 6: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Output Data Timing
The data output of the MT9V011 is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 7: Timing Example of Pixel Data
....
LINE_VALID
....
PIXCLK
Blanking P0 (9:0) P1 (9:0) Valid Image Data P2 (9:0) P3 (9:0) P4 (9:0)
....
Blanking Pn-1 (9:0) Pn (9:0)
DOUT9-DOUT0
....
The rising edges of the PIXCLK signal are nominally timed to occur one-half of a master clock period after the DOUT edges. This allows PIXCLK to be used as a clock to latch the data. The PIXCLK is HIGH for one complete master clock period and then LOW for one complete master clock period. It is continuously enabled, even during the blanking period. The
MT9V011 can be programmed to move the PIXCLK edge relative to the DOUT transitions from +1 to -1 master clock, in steps of one-half of a master clock. This can be achieved by programming the corresponding bits in Reg0x07. The parameters P A, and Q in Figure 8 are defined , in Table 3.
Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
P
A
Q
A
Q
A
P
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Frame Timing Formulas Table 3:
PARAMETER A
Frame Time
NAME Active Data Time EQUATION (Reg0x04 + 1) x (Reg0x0A + 2) DEFAULT TIMING AT 27 MHZ
640 pixel clocks = 1280 master = 47.4s P Frame Start/End Blanking 6 x (Reg0x0A + 2) 6 pixel clocks = 12 master = 0.44s Q Horizontal Blanking (113 + Reg0x05) x (Reg0x0A + 2) 244 pixel clocks (minimum Reg0x05 value = 9) = 488 master = 18.07s A+Q Row Time (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) 884 pixel clocks = 1,768 master = 65.48s V Vertical Blanking (Reg0x06 + 1) x (A + Q) + (Q - 2 x P) 25,868 pixel clocks = 51,736 master = 1.92ms (Reg0x03 + 1) x (A + Q) - (Q - 2 x P) 424,088 pixel clocks Nrows x (A + Q) Frame Valid Time = 848,176 master = 31.41ms F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 449,956 pixel clocks = 899,912 master = 33.33ms
The constant 113 in the formulas in Table 3 is the constant value in default mode, when 8 dark columns are read out through Reg0x30. The constant follows the dark columns read out as shown in Table 4.
Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 7). The recommended master clock frequency is 27 MHz.
Table 4:
1x 01 00
Constant Value
CONSTANT 121 113 107 For 16 columns For 8 columns For no dark columns read, no row-wise noise correction applied
REG 0X30, BIT 1:0
The vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1).
If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 5.
Table 5:
PARAMETER V'
Frame Time - Master Clock
NAME Vertical Blanking (long integration time) Total Frame Time (long integration time) EQUATION (MASTER CLOCK) (Reg0x09 - Reg0x03) x (A + Q) + (Q - 2 x P) DEFAULT TIMING 25,868 pixel clocks = 51,736 master = 1.92 ms 449,956 pixel clocks = 899,912 master = 33.33ms
F'
(Reg0x09 + 1) x (A + Q)
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Serial Bus Description
Registers are written to and read from the MT9V011 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out through the MT9V011 serial data (SDATA) line. The SDATA line is pulled up to VDD off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down--the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16 bits wide, and can be accessed through 16- or eight-bit two-wire serial bus sequences. edge bit after each eight-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V011 allows for eight-bit data transfers through the two-wire serial interface by writing (or reading) the most significant eight bits to the register and then writing (or reading) the least significant eight bits to Reg0x80 (128).
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.
Protocol
The two-wire serial interface defines several different transmission codes, as follows: * a start bit * the slave device eight-bit address * a(n) (no) acknowledge bit * an eight-bit message * a stop bit
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the eight-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9V011 uses 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and eight-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowl-
Slave Address
The eight-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A "0" in the LSB of the address indicates write mode, and a "1" indicates read mode. The write address of the sensor is 0xBA, while the read address is 0xBB.
Data Bit Transfer
One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock--it can only change when the two-wire serial interface clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Interface Sample Read and Write Sequences 16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts the sequence. The image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each eight-bit the image sensor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit.
Figure 9: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg 0x09 ACK 0000 0010 ACK 1000 0100 ACK
STOP
16-Bit Read Sequence
A typical read sequence is shown in Figure 10. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Figure 10: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg 0x09 ACK START 0xBB ADDR ACK 0000 0010 ACK 1000 0100 NACK
STOP
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Eight-Bit Write Sequence
To be able to write one byte at a time to the register a special register address is added. The eight-bit write is done by first writing the upper eight bits to the desired register and then writing the lower eight bits to the special register address (Reg0x80). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 11 a typical sequence for eight-bit writing is shown. The second byte is written to the special register (Reg 0x80).
Figure 11: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK SDATA
0xBA ADDR
Reg0x09
0000 0010
0xBA ADDR
Reg0x80
1000 0100 STOP
START START ACK ACK ACK ACK ACK ACK
Eight-Bit Read Sequence
To read one byte at a time the same special register address is used for the lower byte. The upper eight bits are read from the desired register. By following this
with a read from the special register (Reg0x80) the lower eight bits are accessed (Figure 12). The master sets the no-acknowledge bits shown.
Figure 12: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK SDATA
0xBA ADDR
Reg0x09 START
0xBB ADDR
0000 0010
START
ACK
ACK
ACK
NACK
SCLK SDATA
0xBA ADDR
Reg0x80 START
0xBB ADDR
1000 0100 STOP ACK NACK
START
ACK
ACK
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Registers Register Map Table 6:
0x00/0xFF 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x09 0x0A 0x0B 0x0C 0x0D 0x1E 0x20 0x21 0x22 0x27 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x58 0x59 0x5A 0x5B
Register Map
DESCRIPTION Chip Version Row Start Column Start Window Height Window Width Horizontal Blanking Vertical Blanking Output Control Shutter Width Pixel Clock Speed Restart Shutter Delay Reset Digital Zoom Read Mode Reserved Reserved Reserved Green1 Gain Blue Gain Red Gain Green2 Gain Reserved Reserved Reserved Reserved Reserved Reserved Global Gain Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT (BINARY) 1000 0010 0011 0010 0000 000d dddd dddd 0000 00dd dddd dddd 0000 000d dddd dddd 0000 00dd dddd dddd 0000 00dd dddd dddd 0000 dddd dddd dddd dddd dddd dddd dddd 0000 dddd dddd dddd 0000 0000 000d dddd 0000 0000 0000 000d 0000 00dd dddd dddd 0000 0000 0000 000d 0000 0ddd 0000 00dd dddd dddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd N/A N/A R/O 0x06A0 0x01E0 0x00D1 0x0882 0x0078 0x0703 0x0427 0x0820 0x068F DEFAULT VALUE (HEX) 0x8232 0x000A 0x0016 0x01DF 0x027F 0x0083 0x001C 0x3002 0x01FC 0x0000 0x0000 0x0000 0x0000 0x0000 0x1000 0x0000 0x0000 0x0024 0x0020 0x0020 0x0020 0x0020 0xF7B0 0x0005 0x002A 0x0000 0x300F 0x0100 0x0020
REGISTER # (HEX)
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 6:
0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0xF1 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD
NOTE:
Register Map (continued)
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chip Enable Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT (BINARY) R/O R/O R/O 0000 0000 0000 00dd R/O R/O R/O R/O R/O R/O 0x002C 0xA31D 0x0000 0x0000 0x0418 0x0000 0x0000 0x0000 0x0001 DEFAULT VALUE (HEX)
REGISTER # (HEX)
1 = always 1 0 = always 0 d = programmable ? = read only Do not change reserved register defaults; doing so may put device into an unknown state.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Register Descriptions Table 7:
REGISTER
Register Description
BIT DESCRIPTION
Chip Version 0x00 / 0xFF 0-15 This register is read-only and gives the chip identification number: 0x8232. Window Control These registers control the size of the window. 0x01 0-8 First row to be read out--default = 0x000A (10). Minimum recommended value = 0x0006. 0x02 0-9 First column to be read out--default = 0x0016 (22). Minimum recommended value = 0x0012 (18). 0x03 0x04 0-8 0-9 Window height (number of rows - 1)--default = 0x01DF (479). Window width (number of columns - 1)--default = 0x027F (639). Minimum recommended value = 0x0009.
Blanking Control These registers control the blanking time in a row and between frames. 0x05 0-9 Horizontal Blanking (number of columns)--default = 0x0083 (131 pixel clocks). Minimum value for 0x05 = 0x0009. Minimum recommended value for 0x05 = 0x007B (123 pixel clocks). 0x06 0-11 Vertical Blanking (number of rows -1)--default = 0x001C (28 rows). Minimum recommended value = 0x0003. Output Control This register controls various features of the output format for the sensor. 0x07 0 Synchronize changes (copied to Reg0xF1, bit1). 0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to "0." 1 Chip Enable (copied to Reg0xF1, bit0). 1 = normal operation. 0 = stop sensor readout. When this is returned to "1," sensor readout restarts at the starting row in a new frame. The digital power consumption can then also be reduced to less than 5uA by turning off the master clock. 4 By setting this bit to "1," the sampling and reset timing of the pixels will be halved. This bit should therefore only be used if the master clock frequency is 13.5 MHz or less. When this bit is set the minimum recommended horizontal blanking value is 17, compared to 123 when this bit is not set. Shutter Delay will be master clocks divided by 2 when this bit is set, compared to master clocks divided by 4 when this bit is 0. Note: Use this register for 15 fps with 12 MHz master clock. 5 Allow Shutter Width to be exactly one full frame. 0 = normal operation = Maximum Shutter Width equals the total number of rows - 1. If Shutter Width exceeds the number of rows -1, the total number of rows in the image will be increased to Shutter Width + 1. 1 = Maximum Shutter Width equals the total number of rows. When the Shutter Width exceeds the number of rows, the total number of rows in the image will be increased to match the Shutter Width. 6 Reserved. 8 -11 Shift pixel clock: (11,10,9,8) = (1, x, x, x): shift pixel clock 1 clock earlier (0, 1, x, x): shift pixel clock 1/2 clock earlier (0, 0, 1, x): delay pixel clock by 1/2 clock(0, 0, 0, 1): delay pixel clock by 1 clock (0, 0, 0, 0): no delay pixel clock (default mode). 15 Invert pixel clock: 0 = normal operation. 1 = invert pixel clock.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER
Register Description (continued)
BIT DESCRIPTION
Pixel Integration Control These registers (along with the Window Size and Blanking registers) control the integration time for the pixels. 0x09 0-11 Number of rows of integration, default = 0x01FC (508). 0x0C 0-9 Reset delay, default = 0x0000 (0). This is the number of master clocks x 4 that the timing and control logic waits before asserting the reset for a given row. Pixel Clock Speed 0x0A 4-0 This register determines the pixel data rate, default = 0x0000 (0). Pixel clock period = 2 master clocks + [Reg0x0A, bits (4-0)]. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately. Maximum value for 0x0A = 0x0015. Frame Restart 0x0B 0 Setting bit 0 to "1" of Reg0x0B will cause the sensor to abandon the readout of the current frame and restart from the first row. This register automatically resets itself to 0x0000 after the frame restart. The first frame after this event is considered to be a "bad frame" (see description for Reg0x20, bit 0). Reset (Soft) 0x0D 0 This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a "1" into bit 0 of this register to put the MT9V011 in reset mode, then write a "0" into bit 0 to resume operation. Zoom Mode / True Decimation Mode 0x1E 0 Zoom by 2. 1 Zoom by 4 (if bit 0 is 0). 8 True decimation by 2. Decimate 2x will skip every other column and row, without considering the colors of the pixels. 9 True decimation by 4. Decimate 4x will skip 3 rows/columns for every row/column read out, without considering the colors of the pixels. 10 True decimation by 8. Decimate 8x will skip 7 rows/columns for every row/column read out, without considering the colors of the pixels.
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER
Register Description (continued)
BIT DESCRIPTION
Read Mode This register is used to control many aspects of the readout of the sensor. 0x20 0 Show bad frames: 1 = output all frames (including bad frames). 0 = only output good frames. A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 3 Column skip: 1= read out two columns, and then skip two columns (as with rows). 0 = normal readout. 4 Row skip: 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13...). 0 = normal readout. 9 "Continuous" Line Valid (continue producing line valid during vertical blanking). 0 = Normal Line Valid (default, no line valid during vertical blanking). 10 Line valid = "Continuous" Line Valid XOR Frame Valid. 0 = Normal Line Valid. Ineffective if Continuous Line Valid is set. 11 The four dark rows 0 to 3 are read out in addition to the valid data. 0 = normal readout. To preserve a right-reading image and the correct color order, all four of these bits should be set to "1" to invert the image. 5 1 = readout starting 1 column later. 0 = normal readout. 7 1 = readout starting 1 row later. 0 = normal readout. 14 1 = read out from right to left (mirrored). 0 = normal readout. 15 1 = read out from bottom to top (upside down). 0 = normal readout. Gain Settings The gain can be individually controlled for each color in the Bayer pattern. 0x2B Green1 Gain--default = 0x0020 (32) = 1x gain. 0-6 7, 8 9,10 0x2C 0-6 7, 8 9,10 0x2D 0-6 7, 8 9,10 0x2E 0-6 7, 8 9,10 Initial Gain = bits (6:0) x 0.03125. Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). Blue Gain--default = 0x0020 (32) = 1x gain. Initial Gain = bits (6-0) x 0.03125. Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). Red gain--default = 0x0020 (32) = 1x gain. Initial Gain = bits (6-0) x 0.03125. Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). Green2 gain--default = 0x0020 (32) = 1x gain. Initial Gain = bits (6-0) x 0.03125. Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9, 10: Total gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain).
09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER 0x35 0-6 7, 8 9,10
Register Description (continued)
BIT DESCRIPTION GlobalGain--default = 0x0020 (32) = 1x gain. This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B. Initial Gain = bits (6-0) x 0.03125. Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain).
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Feature Description Window Control
Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and Reg0x04 Window Width (column size) These registers control the size and starting coordinates of the window. By changing these registers, any image format smaller than or equal to VGA can be specified. INT = Reg0x09 x Row Time - Overhead time - Reset delay, where: Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) master clock periods Overhead time = K x 57 master clock periods Reset delay = K x Reg0x0C master clock periods If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will be extended by (K x Reg0x0C - (row time - 444)) clock cycles. Where : K = 4 when Reg0x07[4] = 0, and K = 2 when Reg0x07[4] = 1 In this expression the row time term corresponds to the number of rows integrated. The overhead time is the time between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of Reg0x09 (Shutter Width) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the MT9V011 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60 Hz flicker, this means tINT must be a multiple of 1/120 of a second. Under 50 Hz flicker, t INT must be a multiple of 1/100 of a second.
t
Blanking Control
Reg0x05 Horizontal Blanking, and Reg0x06 Vertical Blanking Blanking Control: These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). * Horizontal blanking is specified in terms of pixel clocks. * Vertical blanking is specified in terms of row readout times. (The programmed value is one less than the actual value.) The actual imager timing can be calculated using Table 3 on page 10 which describes "Row Timing and FRAME_VALID/LINE_VALID Signals." The number of dark rows read out depends on the vertical blanking set as shown in the Table 8.
Table 8:
Vertical Blanking
# DARK ROWS 0 2 4 0 1-2 3+
REG0X06
Pixel Clock Speed
Reg0x0A Pixel Clock Speed The pixel clock speed is set by Reg0x0A. The pixel clock period will be the number set plus two master clock cycles. The default value is 0, which is equal to 2 master clock cycles. With a master clock frequency of 27 MHz the PIXCLK frequency will be 13.5 MHz. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately.
Pixel Integration Control
Reg0x09 Shutter Width, and Reg0x0C Shutter Delay These registers (along with the Window Size and horizontal blanking registers) control the integration time for the pixels. Reg0x09: number of rows of integration, default = 0x01FC (508) Reg0x0C: reset delay, default = 0x0000 (0). This is the number of master clocks that the timing and control logic waits before asserting the reset for a given row. The actual total integration time, tINT, is:
Reset
Reg0x0D Reset This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a "1" into bit 0 of this register, then write a "0" into bit 0 to resume operation.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Digital Zoom
Reg0x1E Digital Zoom/True decimation In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. This is designed to give the controller logic time to repeat data to fill in a window that is either 2 or 4 times larger with repeated data. The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. In zoom by 2 mode, every row is followed by a blank row (with its own line valid, but all data bits = 0) of equal time. In zoom by 4 mode, every row is followed by three blank rows. The combination of this register and an appropriate change to the window sizing registers allows the user to zoom to a region of interest without affecting the frame rate.
Figure 13: Readout of 4 Pixels in Normal and Zoom 2x Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 PIXCLK
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0)
LINE_VALID Zoom 2X readout DOUT9-DOUT0 PIXCLK
G0 (9:0)
R0 (9:0)
G1 (9:0)
R1 (9:0)
True Decimation mode
Reg0x1E Digital Zoom/True decimation True decimation mode is intended for use in sensors without color filtering. There are three modes with different amount of decimation. In decimate 2x every other column and row are skipped. In decimate
4x three rows/columns will be skipped for every row/ column read out, and in decimate 8x seven rows/columns will be skipped for every row/column read out. Decimate 2x is shown in Figure 14. In decimation mode the global gain register should be used to set the gain.
Figure 14: Readout of 8 Pixels in Normal and 2x Decimation Output Mode
LINE_VALID Normal readout DOUT9-DOUT0
P0 (9:0) P1 (9:0) P2 (9:0) P3 (9:0) P4 (9:0) P5 (9:0) P6 (9:0) P7 (9:0)
LINE_VALID Decimate 2X readout DOUT9-DOUT0
P0 (9:0) P2 (9:0) P4 (9:0) P6 (9:0)
Read Mode
Column Mirror image By setting bits 14 and 5 of Reg0x20 the readout order of the columns will be reversed, as shown in Figure 15.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 15: Readout of 6 Pixels in Normal and Column Mirror Output Mode
LINE_VALID Normal readout DOUT9-DOUT0
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0)
Reverse readout DOUT9-DOUT0
G3 (9:0)
R2 (9:0)
G2 (9:0)
R1 (9:0)
G1 (9:0)
R0 (9:0)
Row Mirror Image By setting bits 15 and 7 of Reg0x20 the readout order of the rows will be reversed, as shown in Figure 16.
Figure 16: Readout of 6 Rows in Normal and Row Mirror Output Mode
FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0
Row 6 Row5 Row4 Row3 (9:0) (9:0) (9:0) (9:0) Row2 Row1 (9:0) (9:0) Row0 Row1 Row2 (9:0) (9:0) (9:0) Row3 (9:0) Row4 Row5 (9:0) (9:0)
Column and Row Skip By setting bit 3 of Reg0x20 only half of the columns set will be read out, as shown in Figure 17. The row skip works in the same way and will only read out two
out of four rows. For both row and column skip the number of rows/columns read out will be half of what is set in Reg0x03 and Reg0x04.
Figure 17: Readout of 8 Pixels in Normal and Column Skip Output Mode
L INE_V AL ID Normal readout DOUT9-DOUT0
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) G3 (9:0) R3 (9:0)
L INE_V AL ID Column skip readout DOUT9-DOUT0
G0 (9:0) R0 (9:0) G2 (9:0) R2 (9:0)
Line Valid By setting bit 9 and 10 of Reg0x20 the line valid signal can get three different output formats. The formats are shown in Figure 18 when reading out four rows
and two vertical blanking rows. In the last format the line valid signal is the XOR between the continuously line valid signal and the frame valid signal.
Figure 18: Different Line Valid Formats
Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Recommdended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x35. The analog gain is set by bits[8:0] of the corresponding register as following: Gain = (Bit[8] + 1) x (Bit[7] + 1) x (Bit[6:0]/32) Digital gain is set by bits 9 and 10 of the same registers. The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, while the same overall gain. Table 9 lists the recommended gain settings.
Table 9:
Recommended Gain Settings
RECOMMENDED SETTINGS (GAIN REGISTERS) 0x0020 to 0x003F 0x00A0 to 0x00FF 0x01C0 to 0x01FF CONVERSION FORMULA (ARITHMETIC) (Register value)/32 (Register value - 128)/16 (Register value - 384)/8
DESIRED GAIN 1.000 to 1.969 2.000 to 7.938 8.000 to 15.875
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electrical Specifications Table 10: DC Electrical Characteristics
(VPWR = 2.8 0.25V; TA = Ambient = 25C; 30 fps at 27 MHz) SYMBOL VIH VIL IIN VOH VOL IOH IOL IOZ IAA IDD IAA Standby IDD Standby DEFINITION Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Output High Current Output Low Current Tri-state Output Leakage Current Analog Operating Current Digital Operating Current Analog Standby Supply Current Digital Standby Supply Current CONDITION MIN VPWR-0.25 -0.3 -5 VPWR-0.2 0.2 5.0 5.0 5.0 CLK = 27 MHz; default setting, CLOAD = 10pF CLK = 27 MHz; default setting, CLOAD = 10pF STDBY = VDD STDBY = VDD 14.0 3.0 0.0 0.0 20.0 5.0 0.0 1.0 28.0 8.0 5.0 5.0 TYP MAX VPWR+0.25 0.8 5 UNIT NOTES V V A V V A A A mA mA A A 1 1
No Pull-up Resistor; VIN = VPWR or VGND
NOTE:
1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 11: AC Electrical Characteristics
(VDD = 2.8 0.25V; TA = Ambient = 25C) SYMBOL
fCLK_IN
t t
DEFINITION
Input Clock Frequency Clock Duty Cycle
CONDITION
MIN
45
TYP
27 50 2.5 2.0
MAX
27 55
UNIT
MHz % ns ns ns
NOTES
1
R F
Input Clock Rise Time Input Clock Fall Time CLK_IN to PIXCLK propagation delay: LOW-TO-HIGH HIGH-TO-LOW PIXCLK to DOUT<9:0> Setup Time Hold Time Data Hold Time from CLK_IN CLK_IN to FRAME_VALID and LINE_VALID propagation delay: LOW-TO-HIGH, HIGH-TO-LOW Output propagation delay: LOW-TO-HIGH, HIGH-TO-LOW Output Rise Time Output Fall Time CLOAD = 10pF CLOAD = 10pF
tPLHP, t
PHLP
DVSETUP
12.0 10.0 CLOAD = 10pF, 15.0 14.0 9.0
t
ns ns
tDVHOLD t OH
tPLHFL t
PHLFL PLH PHL
OUTR OUTF
12.0 11.0 CLOAD = 10pF 7.5 7.0 CLOAD = 10pF CLOAD = 10pF 7.0 9.0
ns
t t t t
ns ns ns
NOTE:
1. For 30 fps operation with a 27 MHz clock, it is very important to have a precise duty cycle equal to 50%. With a slower frame rate and a slower clock the clock duty cycle can be relaxed.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Propagation Delays for PIXCLK and Data Out Signals
The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data outputs change on the falling edge of the master clock, with the pixel clock rising on the subsequent rising edge of the master clock. falling master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock falling edge as the end of the output of the last valid pixel's data. As shown in the "Output Data Timing" on page 9, FRAME_VALID goes HIGH 6 pixel clocks prior to the time that the first LINE_VALID goes HIGH. It returns LOW at a time corresponding to 6 pixel clocks after the last LINE_VALID goes LOW.
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same falling master clock edge as the data output. The LINE_VALID goes HIGH on the same
Figure 19: Propagation Delays for PIXCLK and Data Out Signals
tPLHD, tPHLD
CLK_IN
PIXCLK
DOUT (7:0)
tF
tR tF
tR
CLK_IN
tPLHP tPHLP
PIXCLK
tPLHD, tPLHD
tOH
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
Figure 20: Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHFL tPHLFL
CLK_IN
CLK_IN
FRAME_VALID LINE_VALID
tF
FRAME_VALID LINE_VALID
tF
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 21: Data Output Timing Diagram
t FVSETUP
PIXCLK
t t LVSETUP DSETUP t DHOLD t t FTOL t FVHOLD LVHOLD
FRAME_VALID LINE_VALID
DOUT(9:0)
t outR t outF
PIXCLK = max. 27 MHz tFVSETUP = / setup time for FRAME_VALID before rising edge of PIXCLK / = 18 ns tFVHOLD = / hold time for FRAME_VALID after falling edge of PIXCLK / = 18 ns tLVSETUP = / setup time for LINE_VALID before rising edge of PIXCLK / = 18 ns tLVHOLD = / hold time for LINE_VALID after falling edge of PIXCLK / = 18 ns tDSETUP = / setup time for DOUT before rising edge of PIXCLK / = 15 ns tDHOLD = / hold time for DOUT after falling edge of PIXCLK / = 14 ns tFTOL= / FRAME_VALID to LINE_VALID time / = 440 ns
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles.
Figure 24: Serial Host Interface Data Timing for Write
4 SCLK 4
Figure 22: Serial Host Interface Start Condition Timing
5 SCLK 4
SDATA
NOTE:
SDATA is driven by an off-chip transmitter.
SDATA
Figure 25: Serial Host Interface Data Timing for Read Figure 23: Serial Host Interface Stop Condition Timing
SCLK 5 SCLK 4 5
SDATA
SDATA
NOTE: NOTE:
All timing are in units of master clock cycle.
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
Figure 26: Acknowledge Signal Timing After an 8-bit Write to the Sensor
6 SCLK Sensor pulls down SDATA pin 3
SDATA
Figure 27: Acknowledge Signal Timing After an 8-bit Read from the Sensor
7 SCLK Sensor tri-states SDATA pin (turns off pull down) 6
SDATA
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float high. On the following cycle a start or stop bit may be used.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 28: Spectral Response
Relative Spectral Response
1.2
Blue Green (B) Green (R) Red
1.0
Relative Response
0.8
0.6
0.4
0.2
0.0 350
450
550
650
750
850
950
1050
Wavelength (nm)
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 29: Die Placement
11.43mm
Package center
Sensor Chip
Pixel Array 11.43mm Pin 1 Pixel (0,0) Pin 28 Image center
NOTE:
Image center = package center. Not to scale.
Figure 30: Image Center Offset
Image Center Pixel (0,0)
697.4um 14.6um Pixel Array
Chip Center
Sensor Chip
NOTE:
Not to scale.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 31: 28-Pin PLCC Package Outline Drawing
1.70 0.10 2.35 0.15 0.55 0.05 0.350 0.050
1.450 0.075 SEATING PLANE
SECTION A-A
7.62 1.27 TYP 28 1 2.16 0.70 0.05 SUBSTRATE MATERIAL: FR4 RESIN LID MATERIAL: BOROSILICATE GLASS
27X 1.27
29X R0.225 7.62 11.43 0.10
A
A
1.27 TYP 0.64 TYP
8X 1.905 0.100 11.43 0.10
LEAD FINISH: GOLD PLATING, 20 MICRO INCHES MINIMUM THICKNESS 0.08
0.08
Data Sheet Designation
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
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Preliminary
1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Revision History
Rev A, Preliminary ...........................................................................................................................................................4/04 * Initial Release of document
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